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ISL9003A
Data Sheet December 21, 2006 FN6299.1
Low Noise LDO with Low IQ, High PSRR
ISL9003A is a high performance single low noise, high PSRR LDO that delivers a continuous 150mA of load current. It has a low standby current and is stable with 1F of MLCC output capacitance with an ESR of up to 200m. The ISL9003A has a very high PSRR of 90dB and output noise is 20VRMS (typical). When coupled with a no load quiescent current of 31A (typical), and 0.5A shutdown current, the ISL9003A is an ideal choice for portable wireless equipment. The ISL9003A comes in many fixed voltage options with 1.8% output voltage accuracy over temperature, line and load. Other output voltage options are available on request.
Features
* High performance LDO with 150mA continuous output * Excellent transient response to large current steps * Excellent load regulation: <0.1% voltage change across full range of load current * Very high PSRR: >90dB @ 1kHz * Wide input voltage capability: 2.3V to 6.5V * Extremely low quiescent current: 31A * Low dropout voltage: typically 200mV @ 150mA * Low output noise: typically 20VRMS @ 100A (1.5V) * Stable with 1F to 4.7F ceramic capacitors * Shutdown pin turns off LDO with 1A (max) standby current * Soft-start limits input current surge during enable * Current limit and overheat protection
Pinouts
ISL9003A (5 LD SC-70) TOP VIEW
VIN GND EN 1 2 3 4 CBYP 5 VO
* 1.8% accuracy over all operating conditions * 5 Ld SC-70 package or 6 Ld TDFN package * -40C to +85C operating temperature range * Pb-free plus anneal available (RoHS compliant)
ISL9003A (6 LD 1.6x1.6 TDFN ) TOP VIEW
VO GND CBYP 1 2 3 6 5 4 VIN NC EN
Applications
* PDAs, cell phones and smart phones * Portable instruments, MP3 players * Handheld devices including medical handhelds
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2006. All Rights Reserved. All other trademarks mentioned are the property of their respective owners.
ISL9003A Ordering Information
PART NUMBER (Note 2) ISL9003AIENZ-T ISL9003AIEMZ-T ISL9003AIEKZ-T ISL9003AIEJZ-T ISL9003AIEHZ-T ISL9003AIEFZ-T ISL9003AIECZ-T ISL9003AIEBZ-T ISL9003AIRUBZ-T ISL9003AIRUCZ-T ISL9003AIRUFZ-T ISL9003AIRUHZ-T ISL9003AIRUJZ-T ISL9003AIRUKZ-T ISL9003AIRUMZ-T ISL9003AIRUNZ-T NOTES: 1. For other output voltages, contact Intersil Marketing. 2. Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. PART MARKING CBK CBJ CCE CCD CCC CCB CBY CBW L G F H J K M N VO VOLTAGE (V) (Note 1) 3.3 3.0 2.85 2.8 2.75 2.5 1.8 1.5 1.5 1.8 2.5 2.75 2.8 2.85 3.0 3.30 TEMP. RANGE (C) -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 PACKAGE Tape and Reel (Pb-free) 5 Ld SC-70 5 Ld SC-70 5 Ld SC-70 5 Ld SC-70 5 Ld SC-70 5 Ld SC-70 5 Ld SC-70 5 Ld SC-70 6 Ld TDFN 6 Ld TDFN 6 Ld TDFN 6 Ld TDFN 6 Ld TDFN 6 Ld TDFN 6 Ld TDFN 6 Ld TDFN PKG. DWG. # P5.049 P5.049 P5.049 P5.049 P5.049 P5.049 P5.049 P5.049 L6.1.6x1.6A L6.1.6x1.6A L6.1.6x1.6A L6.1.6x1.6A L6.1.6x1.6A L6.1.6x1.6A L6.1.6x1.6A L6.1.6x1.6A
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FN6299.1 December 21, 2006
ISL9003A
Absolute Maximum Ratings
Supply Voltage (VIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.1V All Other Pins . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to (VIN+0.3V)
Thermal Information
Thermal Resistance JA (C/W) 5 Ld SC-70 Package (Note 3) . . . . . . . . . . . . . . . . . 231 6 Ld TDFN Package (Note 4) . . . . . . . . . . . . . . . . 125 Junction Temperature Range . . . . . . . . . . . . . . . . .-40C to +125C Operating Temperature Range . . . . . . . . . . . . . . . . .-40C to +85C Storage Temperature Range . . . . . . . . . . . . . . . . . .-65C to +150C
Recommended Operating Conditions
Ambient Temperature Range (TA) . . . . . . . . . . . . . . .-40C to +85C Supply Voltage (VIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3 to 6.5V
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 3. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 4. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with "direct attach" features. See Tech Brief TB379.
Electrical Specifications
Unless otherwise noted, all parameters are guaranteed over the operational supply voltage and temperature range of the device as follows: TA = -40C to +85C; VIN = (VO+0.5V) to 6.5V with a minimum VIN of 2.3V; CIN = 1F; CO = 1F; CBYP = 0.01F SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
PARAMETER DC CHARACTERISTICS Supply Voltage Ground Current
VIN IDD Output Enabled; IO = 0A; VIN < 4.2V Output Enabled; IO = 0A; Full voltage range
2.3 31
6.5 40 57 0.5 1.2 2.3 2.0 +0.7 +0.8 +1.8
V A A A V V % % % mA
Shutdown Current UVLO Threshold
IDDS VUV+ VUV1.9 1.6 Initial accuracy at VIN = VO+0.5V, IO = 10mA, TJ = +25C VIN = VO+0.5V to 6.5V, IO = 10A to150mA, TJ = +25C VIN = VO+0.5V to 6.5V, IO = 10A to 150mA, TJ = -40C to +125C -0.7 -0.8 -1.8 150 175 IO = 150mA; VO < 2.5V IO = 150mA; 2.5V VO 2.8V IO = 150mA; 2.8V < VO
2.1 1.8
Regulation Voltage Accuracy
Maximum Output Current Internal Current Limit Drop-out Voltage (Note 6)
IMAX ILIM VDO1 VDO2 VDO3
Continuous
265 300 250 200 140 110
355 500 400 325
mA mV mV mV C C
Thermal Shutdown Temperature
TSD+ TSD-
AC CHARACTERISTICS Ripple Rejection (Note 5) IO = 10mA, VIN = 2.8V(min), VO = 1.8V, CBYP = 0.1F @ 1kHz @ 10kHz @ 100kHz Output Noise Voltage (Note 5) VO = 1.5V, TA = +25C, CBYP = 0.1F BW = 10Hz to 100kHz, IO = 100A BW = 10Hz to 100kHz, IO = 10mA DEVICE START-UP CHARACTERISTICS Device Enable TIme LDO Soft-start Ramp Rate TEN TSSR Time from assertion of the EN pin to when the output voltage reaches 95% of the VO(nom). Slope of linear portion of LDO output voltage ramp during start-up 250 30 500 60 s s/V 20 30 VRMS VRMS 90 70 50 dB dB dB
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FN6299.1 December 21, 2006
ISL9003A
Electrical Specifications
Unless otherwise noted, all parameters are guaranteed over the operational supply voltage and temperature range of the device as follows: TA = -40C to +85C; VIN = (VO+0.5V) to 6.5V with a minimum VIN of 2.3V; CIN = 1F; CO = 1F; CBYP = 0.01F (Continued) SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
PARAMETER EN PIN CHARACTERISTICS Input Low Voltage Input High Voltage Input Leakage Current Pin Capacitance NOTES:
VIL VIH IIL, IIH CPIN Informative
-0.3 1.4
0.4 VIN+0.3 0.1 5
V V A pF
5. Guaranteed by design and characterization 6. VO = 0.98 * VO(NOM); Valid for VO greater than 1.85V.
Typical Performance Curves
0.8 0.6 OUTPUT VOLTAGE, VO (%) 0.4 0.2 +25C 0.0 +85C -0.2 -0.4 -0.6 -0.8 3.4 3.8 4.2 4.6 5.0 5.4 5.8 6.2 6.6 INPUT VOLTAGE (V) -40C VO = 3.3V ILOAD = 0mA OUTPUT VOLTAGE CHANGE (%) 0.1 IO = 0mA 0.0 0.2 VO = 3.3V +25C
-0.1
IO = 75mA IO = 150mA
-0.2
-0.3
-0.4 3.3
3.8
4.3
4.8
5.3
5.8
6.3
INPUT VOLTAGE (V)
FIGURE 1. OUTPUT VOLTAGE vs INPUT VOLTAGE (3.3V OUTPUT)
FIGURE 2. OUTPUT VOLTAGECHANGE (%) vs INPUT VOLTAGE (3.3V OUTPUT)
1.0 0.8 OUTPUT VOLTAGE CHANGE (%) 0.6 0.4 0.2 -40C 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 0 25 50 75 100 125 LOAD CURRENT - IO (mA) 150 175 +25C VIN = 3.8V VO = 3.3V OUTPUT VOLTAGE (%)
0.10 0.08 0.06 0.04 0.02 0.00 -0.02 IO = 150mA -0.04 -0.06 -0.08 -0.10 -40 -25 0 25 TEMPERATURE (C) 55 85 IO = 75mA IO = 0mA VIN = 3.8V VO = 3.3V
+85C
FIGURE 3. OUTPUT VOLTAGE vs LOAD CURRENT
FIGURE 4. OUTPUT VOLTAGE vs TEMPERATURE
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FN6299.1 December 21, 2006
ISL9003A Typical Performance Curves (Continued)
3.4 3.3 OUTPUT VOLTAGE, VO (V) VO = 3.3V +25C IO = 0mA IO = 75mA IO = 150mA OUTPUT VOLTAGE, VO (V) 3.2 3.1 3.0 2.9 2.8 2.7 2.6 2.5 2.4 2.3 2.6 3.1 3.6 4.1 4.6 5.1 INPUT VOLTAGE (V) 5.6 6.1 6.6 2.3 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 INPUT VOLTAGE (V) 2.8 2.9
2.7 IO = 0mA 2.6 IO = 75mA IO = 150mA VO = 2.8V +25C 2.4
2.5
FIGURE 5. DROPOUT VOLTAGE vs INPUT VOLTAGE (3.3V OUTPUT)
FIGURE 6. DROPOUT VOLTAGE vs INPUT VOLTAGE (2.8V OUTPUT)
250
225 200 DROP OUT VOLTAGE, VDO (mV) VO = 3.3V +25C +85C
DROP OUT VOLTAGE, VDO (mV)
200
175 150 125 100 75 50 25
150 VO = 2.8V 100 VO = 3.3V
-40C
50
0 0 25 50 75 100 125 OUTPUT LOAD (mA) 150 175
0 0 25 50 75 100 125 150 175 OUTPUT LOAD (mA)
FIGURE 7. DROPOUT VOLTAGE vs LOAD CURRENT
FIGURE 8. DROPOUT VOLTAGE vs LOAD CURRENT
140 120 GROUND CURRENT (A) 100 80 60 40 20 0 0 25 50 75 100 125 150 175 LOAD CURRENT (mA) +85C VIN = 3.8V VO = 3.3V
60
50 GROUND CURRENT (A) +85C 40 +25C 30
+25C
20
10
-40C VO = 3.3V IO = 0A
-40C
0 1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
6.5
INPUT VOLTAGE (V)
FIGURE 9. GROUND CURRENT vs INPUT VOLTAGE
FIGURE 10. GROUND CURRENT vs LOAD
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FN6299.1 December 21, 2006
ISL9003A Typical Performance Curves (Continued)
100 90 80 70 60 50 40 30 20 -40 -30 -20 -10 IL = 75mA VIN = 3.8V VO = 3.3V VEN (V) VO(V) IL = 150mA VIN = 5.0V VO = 3.3V IL = 150mA CL = 1F
GROUND CURRENT (A)
3 2 1 0 5 0
IL = 0mA 0 10 20 30 40 50 TEMPERATURE (C) 60 70 80 90
0
100
200
300
400
500
600
700
800
900 1000
TIME (s)
FIGURE 11. GROUND CURRENT vs TEMPERATURE
FIGURE 12. TURN ON/TURN OFF RESPONSE
VO = 3.3V ILOAD = 150mA CLOAD = 1F CBYP = 0.01F 4.3V 3.6V 4.2V 3.5V
VO = 2.8V ILOAD = 150mA CLOAD = 1F CBYP = 0.01F
10mV/DIV
10mV/DIV
400s/DIV
400s/DIV
FIGURE 13. LINE TRANSIENT RESPONSE, 3.3V OUTPUT
FIGURE 14. LINE TRANSIENT RESPONSE, 2.8V OUTPUT
110 100 VO = 3.3V VIN = 3.8V PSRR (dB) 90 80 ILOAD 100mA 70 60 50 100A VO (10mV/DIV) 20 40 30 VIN = 3.9V VO = 1.8V CBYP = 0.1F CLOAD = 1F 1k 10k FREQUENCY (Hz) 100k 1M 50mA 10mA
1.0 ms/DIV
10 0.1k
FIGURE 15. LOAD TRANSIENT RESPONSE
FIGURE 16. PSRR vs FREQUENCY
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FN6299.1 December 21, 2006
ISL9003A Typical Performance Curves (Continued)
2.000 1.000 SPECTRAL NOISE DENSITY (V/Hz)
0.100
10mA
0.010
VIN = 3.9V VO = 1.8V CBYP = 0.1F CIN = 1F CLOAD = 1F
100A
0.001 10
100
1k 10k FREQUENCY (Hz)
100k
1M
FIGURE 17. SPECTRAL NOISE DENSITY vs FREQUENCY
Pin Description
5 LD SC-70 6 LD TDFN PIN # PIN # PIN NAME 1 2 3 4 5 6 2 4 3 1 5 VIN GND EN CBYP VO NC DESCRIPTION Supply Voltage/LDO Input. Connect a 1F capacitor to GND. GND is the connection to system ground. Connect to PCB Ground plane. Output Enable. When this signal goes high, the LDO is turned on. Reference Bypass Capacitor Pin. Optionally connect capacitor of value 0.01F to 1F between this pin and GND to tune in the desired noise and PSRR performance. LDO Output. Connect a 1F capacitor of value to GND. No Connect.
Typical Application
ISL9003A (SC-70) VIN (2.3-5V) ON ENABLE OFF C1 1 2 3 5 VIN GND EN 4 CBYP VO VOUT
C3
C2
C1, C2: 1F X5R CERAMIC CAPACITOR C3: 0.1F X5R CERAMIC CAPACITOR
VOUT
1 2 3
ISL9003A (TDFN) 6 VO VIN GND CBYP NC EN 5
VIN (2.3-5V) ON
4
ENABLE OFF
C2
C3
C1
C1, C2: 1F X5R CERAMIC CAPACITOR C3: 0.1F X5R CERAMIC CAPACITOR
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FN6299.1 December 21, 2006
ISL9003A Block Diagram
VIN VO
UVLO
CONTROL LOGIC
SHORT CIRCUIT, THERMAL PROTECTION, SOFT-START
GND
+ -
SD
BANDGAP AND TEMPERATURE SENSOR
VOLTAGE AND REFERENCE GENERATOR
1.0V 0.94V 0.9V GND
CBYP
Functional Description
The ISL9003A contains all circuitry required to implement a high performance LDO. High performance is achieved through a circuit that delivers fast transient response to varying load conditions. In a quiescent condition, the ISL9003A adjusts its biasing to achieve the lowest standby current consumption. The device also integrates current limit protection, smart thermal shutdown protection, and soft-start. Smart Thermal shutdown protects the device against overheating. Soft-start minimizes start-up input current surges without causing excessive device turn-on time.
Reference Generation
The reference generation circuitry includes a trimmed bandgap, a trimmed voltage reference divider, a trimmed current reference generator, and an RC noise filter. The filter includes the external capacitor connected to the CBYP pin. A 0.01F capacitor connected CBYP implements a 100Hz lowpass filter, and is recommended for most high performance applications. For the lowest noise application, a 0.1F or greater CBYP capacitor should be used. This filters the reference noise to below the 10Hz - 1kHz frequency band, which is crucial in many noise-sensitive applications. The bandgap generates a zero temperature coefficient (TC) voltage for the regulator reference and other voltage references required for current generation and overtemperature detection. A current generator provides references required for adaptive biasing as well as references for LDO output current limit and thermal shutdown determination.
Power Control
The ISL9003A has an enable pin, EN, to control power to the LDO output. When EN is low, the device is in shutdown mode. In this condition, all on-chip circuits are off, and the device draws minimum current, typically less than 0.3A. When the EN pin goes high, the device first polls the output of the UVLO detector to ensure that VIN voltage is at least 2.1V (typical). Once verified, the device initiates a start-up sequence. During the start-up sequence, trim settings are first read and latched. Then, sequentially, the bandgap, reference voltage and current generation circuitry turn on. Once the references are stable, the LDO powers up. During operation, whenever the VIN voltage drops below about 1.84V, the ISL9003A immediately disables the LDO output. When VIN rises back above 2.1V (assuming the EN pin is high), the device re-initiates its start-up sequence and LDO operation resumes automatically.
LDO Regulation and Programmable Output Divider
The LDO Regulator is implemented with a high-gain operational amplifier driving a PMOS pass transistor. The design of the ISL9003A provides a regulator that has low quiescent current, fast transient response, and overall stability across all operating and load current conditions. LDO stability is guaranteed for a 1F to 4.7F output capacitor that has a tolerance better than 20% and ESR less than 200m. The design is performance-optimized for a 1F capacitor. Unless limited by the application, use of an output capacitor value above 4.7F is not recommended as LDO performance improvement is minimal.
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FN6299.1 December 21, 2006
ISL9003A
Soft-start circuitry integrated into each LDO limits the initial ramp-up rate to about 30s/V to minimize current surge. The ISL9003A provides short-circuit protection by limiting the output current to about 265mA (typ). The LDO uses an independently trimmed 1V reference as its input. An internal resistor divider drops the LDO output voltage down to 1V. This is compared to the 1V reference for regulation. The resistor division ratio is programmed in the factory.
Overheat Detection
The bandgap outputs a proportional-to-temperature current that is indicative of the temperature of the silicon. This current is compared with references to determine if the device is in danger of damage due to overheating. When the die temperature reaches about +140C, the LDO momentarily shuts down until the die cools sufficiently. In the overheat condition, if the LDO sources more than 50mA it will be shut off. Once the die temperature falls back below about +110C, the disabled LDO is re-enabled and soft-start automatically takes place.
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FN6299.1 December 21, 2006
ISL9003A Ultra Thin Dual Flat No-Lead Plastic Package (UTDFN)
E 6 4 A A B
L6.1.6x1.6A
6 LEAD ULTRA THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE MILLIMETERS SYMBOL MIN 0.45 NOMINAL 0.50 0.127 REF 0.15 1.55 0.40 1.55 0.95 0.20 1.60 0.45 1.60 1.00 0.50 BSC 0.25 0.30 0.35 0.25 1.65 0.50 1.65 1.05 MAX 0.55 0.05 NOTES 4 4 Rev. 1 6/06 NOTES: 1. Dimensions are in mm. Angles in degrees. 2. Coplanarity applies to the exposed pad as well as the terminals. Coplanarity shall not exceed 0.08mm.
PIN 1 REFERENCE 2X 0.15 C 1 2X 0.15 C TOP VIEW e 1.00 REF 4 6 3
D
A A1 A3
A1
b D D2
L D2 CO.2 DAP SIZE 1.30 x 0.76
E E2 e L
3 E2
1
b 6X 0.10 M C A B
BOTTOM VIEW
DETAIL A 0.10 C 6X 0.08 C A3 SIDE VIEW C SEATING PLANE
3. Warpage shall not exceed 0.10mm. 4. Package length/package width are considered as special characteristics. 5. JEDEC Reference MO-229. 6. For additional information, to assist with the PCB Land Pattern Design effort, see Intersil Technical Brief TB389.
0.1270.008 0.127 +0.058 -0.008 TERMINAL THICKNESS A1 DETAIL A 0.25 0.50
1.00
0.45
1.00 2.00
0.30
1.25
LAND PATTERN
6
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FN6299.1 December 21, 2006
ISL9003A Small Outline Transistor Plastic Packages (SC70-5)
D
P5.049
VIEW C
e1
5 LEAD SMALL OUTLINE TRANSISTOR PLASTIC PACKAGE INCHES MILLIMETERS MIN 0.80 0.00 0.80 0.15 0.15 0.08 0.08 1.85 1.80 1.15 MAX 1.10 0.10 1.00 0.30 0.25 0.22 0.20 2.15 2.40 1.35 6 6 3 3 4 NOTES -
5 E 1 2 3
4 C L C L E1
SYMBOL A A1 A2 b b1
MIN 0.031 0.000 0.031 0.006 0.006 0.003 0.003 0.073 0.071 0.045
MAX 0.043 0.004 0.039 0.012 0.010 0.009 0.009 0.085 0.094 0.053
e
C L 0.20 (0.008) M C L C
b
c c1
C
D E E1
A
A2
A1
SEATING PLANE -C-
e e1 L L1
0.0256 Ref 0.0512 Ref 0.010 0.018
0.65 Ref 1.30 Ref 0.26 0.46
0.017 Ref. 0.006 BSC 0o 5 0.004 0.004 0.010 8o
0.420 Ref. 0.15 BSC 0o 5 0.10 0.15 0.25 8o
0.10 (0.004) C
L2
WITH PLATING c b b1 c1
5
N R R1 NOTES:
Rev. 2 9/03
BASE METAL
1. Dimensioning and tolerances per ASME Y14.5M-1994.
4X 1 R1 R GAUGE PLANE SEATING PLANE C L1 4X 1 VIEW C L
2. Package conforms to EIAJ SC70 and JEDEC MO-203AA. 3. Dimensions D and E1 are exclusive of mold flash, protrusions, or gate burrs. 4. Footlength L measured at reference to gauge plane. 5. "N" is the number of terminal positions. 6. These Dimensions apply to the flat section of the lead between 0.08mm and 0.15mm from the lead tip. 7. Controlling dimension: MILLIMETER. Converted inch dimensions are for reference only.
L2
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 11
FN6299.1 December 21, 2006

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